Senior Engineer II - Digital Design & Implementation
Salary: RM12,000
Job Description:
The primary responsibilities include, but will not be limited to, architect, develop and implement digital solutions based on design objective specifications. The candidate must be self-motivated, high quality-minded, thorough technical expertise in ASIC design and have excellent communication skills to excel in a global team environment. This position will require driving the development process for the foundation of digital IPs and for digital system integration targeting Microchip’s broad product portfolio of complex Analog-Mixed-Signal embedded semiconductor solutions.
The Analog Power and Interface Division (APID) focuses on delivering a portfolio of solutions in the areas of Power Management, Automotive In-Vehicle Network CAN/LIN, Motor Drive, USB Port Power Switches, High Voltage Driver, Medical Ultrasound, and Power over Ethernet.
Responsibilities:
Ownership of functional blocks and major sub-systems and contribute through various phases of the ASIC design process – Micro-architecture specification, RTL design, simulation and front-end implementation.
Perform synthesis, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level.
Writing block level Verilog/System-Verilog directed test-benches and overall verification enablement.
Interface and work with local and remote teams to meet area, power, and performance requirements for macro under development.
Present status on progress, risk and schedule to stakeholders in a timely fashion.
Train and mentor junior digital design engineers locally.
Requirements/Qualifications:
Experienced engineer with BSEE with at least 5+ years of ASIC development experience are preferable:
BSc/MSc in EE or Computer Science
Must be proficient in design flow such as micro-architecture, RTL coding, debugging, simulation, clocks and constraints for synthesis and static timing analysis (STA)
Understand Design-For-Test concepts and methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation)
Able to run formal verification/equivalence checking, Linting and CDC checking
Scripting skills in any programming language (preferably Perl, TCL and Shell) is a plus
Knowledge of UVM based verification and code coverage is a plus
Able to work independently and provide local mentorship as a project lead / supervisor
Ability in debugging, problem solving and analytical skills
Strong verbal and written communication skills
Apply on website or send your resume to Joseph: [email protected]