Senior Engineer I – Analog Design

Location Malaysia
Discipline Engineering
Job reference 165648
Salary 12000.0
Consultant name Joseph Barik
Contact email [email protected]
Contact name Joseph Barik
Contact email [email protected]

Senior Engineer I – Analog Design
​​​​​​​Salary: RM12,000

Job Description:

We are seeking an individual with mixed signal design or verification experience to expand this group and build advanced high-speed SERDES and PHY designs in FinFET technologies. A candidate in this position is expected to take the lead, drive issue resolution, recommend and implement Industry best practices for Front End Verification as well as develop Tools, Flows and Methodologies required to make the team a Center of Excellence.

Responsibilities:

  • Playing the role of a Verification Lead and driving the team to achieve project verification goals.
  • Understanding design changes, developing comprehensive Verification Testplan.
  • Developing and/or enhancing testbench or verification components such as UVCs, models, BFMs, with a priority on re-usability of UVCs.
  • Driving the verification culture of the team in how to design, develop and maintain UVM testbench, tests and sequences.
  • Define and develop verification process improvements and methodologies as part of continuous improvement
  • Familiarity with industry front end verification CAD tools.
  • Ability to coach, guide and nurture junior engineers.
  • Work cross-site with Global team.

Requirements/Qualifications:

  • Bachelor’s or higher degree in Electrical Engineering
  • Work experience: 8+ years in ASIC Verification background
  • Experience in digital design with solid, hands-on experience in Functional Design Verification and UVM/OVM Methodology.
  • Experience in developing a vertically and horizontally scalable testbench will be an added benefit.
  • Experience in high-speed SERDES PHY, PCIE or familiarization with serial protocols will be a strong plus-point
  • Must have excellent debug skills in both functional and gate level simulations.
  • Familiarity with industry CAD tools
  • Previous experience in writing/implementing/reviewing test plans
  • Experience in verifying Mixed Signal simulations will be an asset
  • Experience in automation and scripting with languages such as Python/Perl/TCL/Shell
  • Strong working knowledge of Verilog, SystemVerilog

Apply on website or send your resume to Joseph: [email protected]