Principal Engineer - Design

Location Malaysia
Discipline Engineering
Job reference 165649
Salary 18000.0
Consultant name Joseph Barik
Contact email [email protected]
Contact name Joseph Barik
Contact email [email protected]

Principal Engineer - Design

Job Description:

As a Principle Design Implementation engineer, the candidate will be supervised by a local manager, be engaged into projects to perform the synthesis, DFT implementation, timing closure and ensure the design is implemented correctly with various checks/verification/audit. Also, be involved in design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology.

Responsibilities:

  • Own block/sub-system level and potentially chip level design implementation from RTL to gate-level netlist and driving for design closure sign-off.
  • Develop synthesis plan with Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) in developing design constraints for implementation to meet timing closure, area, power, and performance requirements.
  • Implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
  • Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements

 

Requirements/Qualifications:

 

This position requires at least BSEE with 8-12 years of ASIC development experience in a fast paced environment. You are required to have expertise in a wide range of areas in design implementation, tools and flows:

  • BEng/MEng in EE or Computer Science with the completion of several complex ASIC or IC tapeouts in VDSM process technology nodes.
  • Design and Synthesis experience in high performance design (high speed / low power) is a must. State of the art knowledge of semi-custom design & implementation tools
  • Experienced with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization and Logic Equivalency Check
  • Experience in synthesis algorithms, best RTL coding for synthesis, low-power and high-speed design trade-offs, physical aware' synthesis, deep sub-micron process effects
  • Understand Design-For-Test tools (Tetramax, DFT Advisor) & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation).
  • Understand JTAG IEEE standard for board level connections testing and/or enable block level DFT testing is a plus.
  • Experienced in Static Timing Analysis tools/flows (e.g. Prime Time, Tempus or equivalent) and constraint checkers.
  • Experienced in auto Place & Route (APR) tools/flows (e.g. ICC/ICC2, Innovus or equivalent).
  • Good scripting skills in Perl, TCL and Shell, particularly in synthesis & timing algorithms, with solid understanding of UNIX/LINUX.
  • Working knowledge of RTL coding
  • Low power methodologies and impact on overall design goals.
  • Able to work autonomously as well as in a team environment across multiple geographical sites, with a strong desire to succeed.
  • Excellent debugging, problem solving and analytical skills.
  • Excellent verbal and written communication skills. Strong interpersonal skills.
  • Have lead and mentor others and work under challenging environment.

Apply on website or send your resume to Joseph: [email protected]